%0 Journal Article %T Analytic modeling of breakdown voltage shift in the CMOS buried multiple junction detector %+ INL - Lab-On-Chip et Instrumentation (INL - LOCI) %+ INL - Conception de Systèmes Hétérogènes (INL - CSH) %A Vidal de Negreiros da Silva, Thais Luana %A Kleimann, Pascal %A Pittet, Patrick %A Lu, Guo-Neng %< avec comité de lecture %@ 0038-1101 %J Solid-State Electronics %I Elsevier %V 164 %P 107682 %8 2020-02 %D 2020 %R 10.1016/j.sse.2019.107682 %Z Engineering Sciences [physics]/ElectronicsJournal articles %G English %2 https://univ-lyon1.hal.science/hal-02463250/document %2 https://univ-lyon1.hal.science/hal-02463250/file/S0038110119302047.pdf %L hal-02463250 %U https://univ-lyon1.hal.science/hal-02463250 %~ CNRS %~ UNIV-LYON1 %~ INSA-LYON %~ EC-LYON %~ INL %~ PRIMES %~ PRIMES_WP1 %~ INSA-GROUPE %~ UDL %~ UNIV-LYON %~ TEST-HALCNRS %~ ELSEVIER